The invention relates to a signal processing system including both analog and digital processing circuits, and more particularly, to a signal processing system with noise suppression.
Conventional signal processing circuits used for processing an image signal and an aural signal have been analog systems, such processing circuits are now transitioning to digital systems. For example, in an image sensor system, an analog image signal from an image sensor is converted to digital image data via A/D conversion, and is then acted upon by a signal processing circuit.
An image sensor system which employs conventional digital signal processing is shown in FIG. 1. As shown, the system comprises a CCD image sensor 1, a drive circuit 2, a timing control circuit 3, an analog processing circuit 4, an A/D converter 5 and a digital processing circuit 6.
The CCD image sensor 1 includes a plurality of light receiving pixels, not shown, which are disposed in a matrix array on a light responsive surface, and a plurality of shift registers, also not shown, connected to respective light receiving pixels to read an information charge stored therein in a predetermined sequence. A light receiving pixel comprises a photodiode, for example, which produces and stores the information charge in accordance with an image of a photographed object formed on the light responsive surface. Generally, the shift registers include a plurality of vertical transfer shift registers and a single horizontal transfer shift register. Each vertical transfer shift register is aligned with each column of the array of pixels, and the horizontal transfer shift register receives respective outputs from the plurality of vertical transfer shift registers in parallel at its individual stages.
The timing control circuit 3 generates a vertical timing signal VD and a horizontal timing signal HD, which determine the timing of a vertical scan and a horizontal scan, respectively, in accordance with a reference clock signal BCK having a predetermined period. For example, for the NTSC system, the timing control circuit 3 receives the reference clock signal BCK having a frequency of 14.32 MHz, and generates the vertical timing signal VD by a frequency demultiplication of the reference clock signal BCK by a factor of 910 and generates the horizontal timing signal HD by a frequency demultiplication of the vertical timing signal by a factor of 525 combined with a multiplication by a factor of 2. The timing control circuit 3 also controls the operational timings of the circuits 4 to 6 so that their operations are synchronized with the operation of the image sensor 1.
The drive circuit 2 generates a multi-phase vertical transfer clock signal xcfx86V and a multi-phase horizontal transfer clock signal xcfx86H in response to the vertical timing signal VD and the horizontal timing signal HD supplied from the timing control circuit 3. The vertical transfer clock signal xcfx86V is fed to the vertical transfer shift registers in the image sensor 1 simultaneously. Accordingly, the information charge stored in the plurality of pixels in one row is transferred to initial stages of the vertical transfer shift registers and then sequentially shifted from stage to stage in the latter in accordance with the vertical transfer clock signal xcfx86V, and is subsequently transferred from the final stages of the vertical transfer shift registers to the horizontal transfer shift register in accordance with the horizontal timing signal HD. The horizontal transfer clock signal xcfx86H is fed to the horizontal transfer shift register, whereby the information charge, which is transferred from the vertical to the horizontal transfer shift register, is delivered pixel by pixel in accordance with the horizontal transfer clock signal xcfx86H. As a result, the image information for one frame is delivered from the image sensor 1 to the analog processing circuit 4 in the form of an image signal Y0(t) which is contiguous from row to row.
The analog processing circuit 4 receives the image signal Y0(t), which will be hereafter referred to as the first analog signal, and performs processing, such as sample-and-hold and level clamping operations thereto to form a second analog signal Y1(t) which conforms to a predetermined format. Where the image signal includes an alternation between a reset level and a signal level, the sample-and-hold operation takes place, for example, in a manner such that only the signal level is derived from the first analog signal Y0(t) in synchronism with its delivery from the image sensor 1. During the level clamping operation, the black reference level, which is set at the end of a horizontal scan period for the first analog signal Y0(t), is clamped to a predetermined level for every horizontal scan period.
The A/D converter 5 normalizes the second analog signal Y1(t) received from the analog processing circuit 4 according to the timing of the analog processing circuit 4 or the timing which controls the delivery from the image sensor 1, and produces first digital data D0(n) representing the information corresponding to individual pixels in the image sensor 1. The digital processing circuit 6 receives the first digital data signal D0(n) from the A/D converter 5 and produces second digital data D1(n) containing luminance information and color difference information by performing prescribed operations, such as a color separation and a matrix operation on the first digital data D0(n). For example, during the color separation, the first digital data D0(n) is apportioned according to an array of color filters mounted on the light responsive surface of the image sensor 1, thus producing information representing a plurality of color components. The luminance information is produced by a synthesis of apportioned color components and color difference information is produced by subtracting the luminance information from respective color component information during the matrix operation.
The process of producing color components is little influenced by noise because of the matrix operation. However, processing of analog signals such as an image signal and an aural signal cannot be entirely digitalized, and accordingly, the image sensor system requires both of the analog processing circuit 4 and the digital processing circuit 6. When an integration of both the analog processing circuit 4 and the digital processing circuit 6 on a common semiconductor substrate is implemented, there is a need to suppress the influence of noise, which may be produced in the digital processing circuit 6, upon the analog processing circuit 4. One remedy to guard against noise is for the digital processing circuit 6 to a use Gray code counter instead of a binary counter which is liable to produce noise having a periodicity. It is noted that the Gray code counter has a predetermined number of bits which change from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d or from xe2x80x9c1xe2x80x9d to xe2x80x9c0xe2x80x9d.
When the digital processing circuit 6 is integrated on the same substrate as the analog processing circuit 4, a processed digital signal from the circuit 6 is delivered to an external circuit via an output buffer. The output buffer contains transistors of relatively large sizes in order to drive an external load. Accordingly, as digital data is delivered via the output buffer, it is likely that noises are irregularly produced in response to changes in the output signal. Hence, if the integration of both of the processing circuits 4 and 6 on the common substrated is implemented, such noises may find their way into the analog processing circuit 4 to disturb its signal.
If the analog processing circuit 4 and the digital processing circuit 6 are integrated on separate substrates, when the circuits 4, 6 are operated from a common power supply, noises produced in the digital processing circuit 6 may again find their way into the analog processing circuit 4 via the power supply.
It is an object of the present invention to provide a signal processing system which suppresses noise generated within a digital processing circuit thereof.
In one aspect of the present invention, a signal processing system includes an analog processing circuit for performing a predetermined signal processing operation on an analog input signal. An A/D converter is connected to the analog signal processing circuit for receiving a processed analog signal from the analog signal processing circuit and for converting the processed analog signal into at least one digital data having at least one bit. A complementary data generating circuit receives the digital data from the A/D converter and produces sub-data containing at least one bit which is mutually complementary to the digital data. The complementary data generating circuit is operative whenever there is a change in at least one bit between consecutive bits of the digital data to maintain the status of a corresponding bit in the sub-data unchanged, and whenever there is no change in at least one bit between consecutive bits of the digital data to invert a corresponding bit in the sub-data. A first output circuit is connected to the complementary data generating circuit for delivering the digital data. A second output circuit is connected to the complementary data generating circuit for delivering the sub-data.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.